Introduction

REFLECT stands for Rendering FPGAs to Multi-Core Embedded Computing.

The relentless increase in capacity of Field-Programmable Gate-Arrays (FPGAs) has made them vehicles of choice for both prototypes and final products of on-chip multi-core, heterogeneous and reconfigurable systems. Multiple cores can be embedded as hard- or soft-cores, have customizable instruction sets, multiple distributed RAMs and/or configurable interconnections. Their flexibility allows them to achieve orders of magnitude better performance than conventional computing systems via customization. Programming these systems, however, is extremely cumbersome and error-prone hampering their widespread adoption and limiting their true computational potential.

Technology Description

The REFLECT project is developing, implementing and evaluating a novel compilation and synthesis system approach for FPGA-based platforms. The approach relies on Aspect-Oriented Specifications to convey critical domain knowledge to all development steps.

Project Objectives

• Improve productivity

  • Accelerating design cycles by more than two orders of magnitude
  • Allow user to have full control in a consistent, systematic way of development flow stages

• Bring to development flow

  • User’s knowledge about the algorithm
  • Non-functional requirements
  • Flexibility to define properties of target FPGA and memory organization
  • Best design practices represented by design patterns and HW/SW templates

REFLECT’s Repository of Applications

• Avionics: 3D Path Planning, and Stereo Navigation
• Audio: MPEG audio encoder, and G729 voice encoder

Technical Plan

• Analyze applications to identify suitable aspects, design patterns and HW/SW templates, as well as reconfiguration schemes
• Develop techniques for configuration and reconfiguration based on the REFLECT’s aspect-oriented concept
• Develop aspects, design patterns, and HW/SW templates
• Specify new intermediate representation that supports orthogonal views, e.g., CDFG-view and Aspect-view
• Develop techniques for data type and word-length optimizations
• Develop techniques for automatic HW generation
• Develop techniques for cost effective mapping of computations to reconfigurable hardware, e.g. FPGAs by means of a domain specific language (LARA)
• Develop unqualified development tools
• Evaluate and validate

Advances over State-of-the-art

The REFLECT’s approach intends to solve some of the problems when mapping efficiently computations to FPGA-based systems. In particular, the use of aspects and strategies will allow developers to try different design patterns and to achieve solutions design-guided by non-functional requirements. To the best of our knowledge, the REFLECT design flow is the first approach considering a systematic control of all the compilation stages and the first one to consider the relationship between non-functional requirements to different design patterns and optimizations, both specified in a domain-specific language, named LARA.

Expected Results

• Enable one application, multiple designs according to different customer requirements with reduced V&V cost and overall development cost
  • In a traceable way through the notation of Requirements-Aspects-Design Patterns-HW templates
  • With pre-verified Design Patterns and HW Templates
• Systematic approach to Guide Design Flow Stages
  • Limiting design space given requirements and derived aspect
  • Bringing an opportunity to achieve cost-effective designs
• Allow Specification of Reusable Design Patterns and Best Practices
  • Capture and codify application and platform specific knowledge and expertise.

Team

Zlatko Petrov and Kamil Krátký (Honeywell), Pedro C. Diniz and Ricardo Nobre (INESC-ID), João M.P. Cardoso, José Carlos Alves, and João Canas Ferreira, Tiago Carvalho (UPORTO), Koen Bertels, Georgi Kuzmanov, Razvan Nane, and Vlad-Mihai Sima (TUD), Jürgen Becker, Michael Hübner, Florian Thoma, Lars Braun, and Matthias Kühnle (KIT), George Constantinides, Wayne Luk, José Gabriel de F. Coutinho, and Sujit Bhattacharya (ICSTM), Bryan Olivier and Hans van Someren (ACE), Fernando Gonçalves (CW)

Acknowledgment

This work was partially supported by the European Community under the Framework Programme 7 (FP7) under contract No. 248976.

Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the European Community.

 

Application-Specific Multi-Core Architectures

Reconfigurable Computing Systems

Aspect-Oriented Specifications